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AT42QT1111-MU Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT42QT1111-MU Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 50 page  39 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 8.5 SPI Bus Specifications 8.5.1 General Specifications 8.5.2 Full SPI Mode 8.5.3 Quick SPI Mode Parameter Specification Address space 8-bit Maximum clock rate 750 KHz Minimum low clock period 666 ns Minimum high clock period 666 ns Clock idle High Setup on Leading (falling) edge Clock out on Trailing (rising) edge SPI Enable delay (SS low to SCK low) 1 µs Parameter Specification Time between bytes 300 µs Time between communications Generally 300 µs; longer delays required to implement some commands, as follows: • Send Setups: 300 µs after all setup bytes are returned • Calibrate All: 300 µs • Calibrate Key: 300 µs • Reset: 320 ms • Sleep: 300 µs after a low signal is applied to SS or CHANGE to wake the device • Store to EEPROM: 200 ms • Restore from EEPROM: 150 ms • Erase EEPROM: 50 ms • Recover EEPROM: 50 ms Parameter Specification Time between bytes 100 µs Time between communications Generally 100 µs, except for the following: • Store to EEPROM: 200 ms • Switch to Full SPI: 300 µs |
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