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TMS320DM8148_1109 Datasheet(PDF) 15 Page - Texas Instruments |
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TMS320DM8148_1109 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 360 page  Instruction Fetch C674x Fixed/Floating Point CPU Register File A Register File B Cache Control Memory Protect Bandwidth Mgmt L1P 256 Cache Control Memory Protect Bandwidth Mgmt L1D 64 64 8 x 32 32K Bytes L1D RAM/ Cache 32K Bytes L1P RAM/ Cache w/EDC 256 Cache Control Memory Protect Bandwidth Mgmt L2 256K Bytes L2 RAM w/ ECC 256 HDVICP2 Host SL2 Port 256 CFG MDMA SDMA EMC Power Down Interrupt Controller IDMA 256 256 256 256 256 128 L3 (Fast) Interconnect 128 32 L3 (Fast) Interconnect TMS320DM8148, TMS320DM8147, TMS320DM8146 www.ti.com SPRS647B – MARCH 2011 – REVISED SEPTEMBER 2011 2.5 C674x ™ DSP Overview The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Circuitry (EDC) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 256KB Unified Mapped RAM/Cache (L2) with Error Correction Circuitry (ECC) • Direct Connection to the HDVICP2 Host SL2 Port • Little Endian Figure 2-2. C674x Megamodule Block Diagram Copyright © 2011, Texas Instruments Incorporated Device Overview 15 Submit Documentation Feedback Product Folder Link(s): TMS320DM8148 TMS320DM8147 TMS320DM8146 |
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