AFS090 datasheet(242/334 Pages) MICROSEMI

242 / 334 page

Device Architecture

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R e v isio n 2

pump, and eNVM operation. VCCOSC is off only when VCCA is off. VCCOSC must be powered

whenever the Fusion device needs to function.

VCC

Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is also required for powering the JTAG state

machine, in addition to VJTAG. Even when a Fusion device is in bypass mode in a JTAG chain of

interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass

through the Fusion device.

VCCIBx

I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are either

four (AFS090 and AFS250) or five (AFS600 and AFS1500) I/O banks on the Fusion devices plus a

dedicated VJTAG bank.

Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply.

VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their

corresponding VCCI pins tied to GND.

VCCPLA/B

PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V, where A and B refer to the PLL. AFS090 and AFS250

each have a single PLL. The AFS600 and AFS1500 devices each have two PLLs. Microsemi

recommends tying VCCPLX to VCC and using proper filtering circuits to decouple VCC noise from PLL.

If unused, VCCPLA/B should be tied to GND.

VCOMPLA/B

Ground for West and East PLL

VCOMPLA is the ground of the west PLL (CCC location F) and VCOMPLB is the ground of the east PLL

(CCC location C).

VJTAG

JTAG Supply Voltage

Fusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives

greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is

neither used nor planned to be used, the VJTAG pin together with the TRST pin could be tied to GND. It

should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a

Fusion device is in a JTAG chain of interconnected boards and it is desired to power down the board

containing the Fusion device, this may be done provided both VJTAG and VCC to the Fusion part remain

powered; otherwise, JTAG signals will not be able to transition the Fusion device, even in bypass mode.

VPUMP

Programming Supply Voltage

Fusion devices support single-voltage ISP programming of the configuration flash and FlashROM. For

programming, VPUMP should be in the 3.3 V +/-5% range. During normal device operation, VPUMP can

be left floating or can be tied to any voltage between 0 V and 3.6 V.

When the VPUMP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

User-Defined Supply Pins

VREF

I/O Voltage Reference

Reference voltage for I/O minibanks. Both AFS600 and AFS1500 (north bank only) support Microsemi

Pro I/O. These I/O banks support voltage reference standard I/O. The VREF pins are configured by the

user from regular I/Os, and any I/O in a bank, except JTAG I/Os, can be designated as the voltage

reference I/O. Only certain I/O standards require a voltage reference—HSTL (I) and (II), SSTL2 (I) and

(II), SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support the number of I/Os available in its

minibank.

AFS090 Datasheet(PDF) 242 Page - Microsemi Corporation

AFS090 Datasheet(HTML) 242 Page - Microsemi Corporation

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