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AK4160 Datasheet(PDF) 21 Page - Asahi Kasei Microsystems |
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AK4160 Datasheet(HTML) 21 Page - Asahi Kasei Microsystems |
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21 / 40 page  [AK4160] MS1313-E-01 2011/11 - 21 - Address 0x03 (W/R) Default 0x00 Description D7 D6 D5 D4 D3 D2 D1 D0 IRQ Status IOVER Reserved Reserved Reserved Reserved IRQ2 IRQ1 IRQ0 Bits Name Description D7 IOVER Short Detection of the RREF pin The IOVER bit is set to “1”, when the RREF pin is shorted to VSS in run mode. The AK4160 is changed from run mode to shutdown mode for the over current protection. The IRQ bit setting to the edge action is fix to the active state. When the IOVER bit is “1”, run mode is invalid. When the IOVER bit is written “1”, the IOVER bit or IRQ2-0 bits are cleared. D6-D3 Reserved Reserved: Must write “0” D2-D0 IRQ2-0 IRQ Status · The Edge Action case The IRQ bits are set to “1”, when an interrupt occurs. There are 2ways to clear these bits. It is selected by CLRM bit in the IRQCn register. CLRM bit = “0”: When the lower byte of the IRQ Status register is read. CLRM bit = “1”: When the related bit (IRQ2-0 bits) is written “1”, the bit is cleared · The Level Action case The IRQ bits are set to the input level of IRQN2-0 terminals. Reading or writing “1” to the IRQ bits is invalid. · The GPIO Function The IRQ bits are set to the level of IRQN2-0 terminals. Reading or writing “1” to the IRQ bits is invalid. |
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