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AK4160 Datasheet(PDF) 26 Page - Asahi Kasei Microsystems |
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AK4160 Datasheet(HTML) 26 Page - Asahi Kasei Microsystems |
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26 / 40 page  [AK4160] MS1313-E-01 2011/11 - 26 - GPIO Output Control Register Address 0x35/0x37/…/0x43 (W/R) Default 0x00 Description D7 D6 D5 D4 D3 D2 D1 D0 GPIO Output Control DIR REL SRC[1] SRC[0] DRV[1] DRV[0] INV DSTR Address 0x36/0x38/…/0x44 (W/R) Default 0x00 Description D7 D6 D5 D4 D3 D2 D1 D0 GPIO Output Control PWM PRD[1] PRD[0] DUTY[4] DUTY[3] DUTY[2] DUTY[1] DUTY[0] Bits Name Description D7 DIR This bit should be set to “1” at the output setting of GPIO. D6 REL The Output Setting (SRC1-0 bits = “01”, “10”, “11”) 0: Touch Status 1: Release Status D5-D4 SRC The Selection of Output Data 00: The value set by GPDT register (Addr 0x5D) is output. 01: The status value set by REL bit is output. 10: The status value set by REL bit is output in the toggle. (Initial value 0) 11: The status value set by REL bit is output in the toggle. (Initial value 1) When the touch status (release status) is selected as output data, the terminal GPIOn outputs the status of terminal CSn (n=0~7). Touch status is recognized as “0” at shutdown mode. The output value is initialized by writing “0” to corresponding GPDT register (Addr 0x5D) when SRC1-0 bits = “01”, “10”, “11”. 01: The output value is initialized by “0”. 10: The output value is initialized by “0”. 11: The output value is initialized by “1”. D3-D2 DRV Output Driver Setting 00: CMOS Output 01: Low Side Output: When Output is “H”, Hi-z (Open Drain) 10: High Side Output: When Output is “L”, Hi-z (Open Drain) 11: CMOS Output (Same as 00 Setting) D1 INV The output level is reversed. D0 DSTR The Driving ability of the GPIO output driver is set. 0: 1/3 drive 1: full drive Bits Name Description D7 PWM PWM Output Enable D6-D5 PRD Cycle of the PWM output is set. 00: 125Hz 01: 250Hz 10: 500Hz 11: 1000Hz D4-D0 DUTY Duty of the PWM output is set. Duty=(DUTY + 1) / 32: 1/32 ~ 32/32 Refer to Table 7 for the correspondence of the register address and the GPIO pin. |
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