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AK4160 Datasheet(PDF) 7 Page - Asahi Kasei Microsystems

Part # AK4160
Description  16-channel Capacitive Touch Sensor IC
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AK4160 Datasheet(HTML) 7 Page - Asahi Kasei Microsystems

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[AK4160]
MS1313-E-01
2011/11
- 7 -
SWITCHING CHARACTERISTICS
(Ta = -40
°C ~ 85°C, VDD = 1.71V ~ 3.6V; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Touch Sensor
Charge Time (Note 16)
TCHG
-15
-
15
%
Sampling Rate (Note 17)
TSR
-35
-
35
%
PWM
Frequency Accuracy
ACCF
-35
-
35
%
Reset Timing
Reset Pulse Width (Note 18)
tRSTN
10
-
-
us
Reset Pin Pulse Width of Spike Noise
Suppressed by Input Filter (Note 19)
tRSTNS
0.5
-
-
us
Start Up Timing
Power up time (Note 20)
tPU
-
-
1
ms
Power up rise time
tPR
-
-
20
ms
Power up Interval time (Note 21)
tPI
20
-
-
ms
I2C
SCL clock frequency
fSCL
-
-
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
-
μs
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
0.6
-
-
μs
Clock Low Time
tLOW
1.3
-
-
μs
Clock High Time
tHIGH
0.6
-
-
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
μs
SDA Hold Time from SCL Falling (Note 22)
tHD:DAT
0
-
-
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
-
-
μs
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
50
-
-
ns
Capacitive load on bus
Cb
-
-
400
pF
Note 16. Variation against nominal value of TCHG (0.25us to 32us)
Note 17. Variation against nominal value of TSR (4ms to 512ms)
Note 18. The AK4160 can be reset by the RSTN pin = “L”. This is to initialize the AK4160 for sure.
Note 19. Pulse width of spike noise suppressed by input filter of the RSTN pin.
Note 20. Time as the starting point when reached VDD=1.71V and VREG=1.0V, with CREG=47nF.
Note 21. The condition of “VDD=VSS” should be kept during the Power up Interval Time.
Note 22. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
VIL
RSTN
tRSTN
tRSTNS
Figure 2. Reset Timing Diagram


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