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ADIS16488 Datasheet(PDF) 22 Page - Analog Devices |
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ADIS16488 Datasheet(HTML) 22 Page - Analog Devices |
22 / 36 page ADIS16488 Data Sheet Rev. B | Page 22 of 36 Table 62. Filter Bank D Memory Map Page PAGE_ID Address Register 11 0x0B 0x00 PAGE_ID 11 0x0B 0x02 to 0x07 Not used 11 0x0B 0x08 FIR_COEF_D000 11 0x0B 0x0A FIR_COEF_D001 11 0x0B 0x0C to 0x7C FIR_COEF_D002 to FIR_COEF_D058 11 0x0B 0x7E FIR_COEF_D059 12 0x0C 0x00 PAGE_ID 12 0x0C 0x02 to 0x07 Not used 12 0x0C 0x08 FIR_COEF_D060 12 0x0C 0x0A FIR_COEF_D061 12 0x0C 0x0C to 0x7C FIR_COEF_D062 to FIR_COEF_D118 12 0x0C 0x7E FIR_COEF_D119 Default Filter Performance The FIR filter banks have factory-programmed filter designs. They are all low-pass filters that have unity dc gain. Table 63 provides a summary of each filter design, and Figure 21 shows the frequency response characteristics. The phase delay is equal to ½ of the total number of taps. Table 63. FIR Filter Descriptions, Default Configuration FIR Filter Bank Taps −3 dB Frequency (Hz) A 120 310 B 120 55 C 32 275 D 32 63 NO FIR FILTERING 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 200 400 600 800 1000 1200 FREQUENCY (Hz) A D C B Figure 21. FIR Filter Frequency Response Curves |
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