Sensors

26

Freescale Semiconductor, Inc.

MMA16xxKW

3.5.3.3

Compensation

The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.

3.5.3.4

Data Interpolation

The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital

signal processing chain is delayed one sample time. On reception of an acceleration data request, the transmitted data is inter-

polated from the two previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample

3.5.3.5

Output Scaling

The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-Bit word which covers the acceleration range of

Figure 18. Output Scaling Diagram

3.5.3.6

PCM Output Function

The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2

register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the accel-

eration response is output onto the PCM pin. The PCM output is intended for test use only. A block diagram of the PCM output

Figure 19. PCM Output Function Block Diagram

Over Range

Signal

Noise

Margin

D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10

D9

D8

...

D2

D1

D0

10-Bit Data Word

D21 D20 D19 D18 D17 D16 D15 D14 D13 D12

Using Truncation

9-Bit Data Word

D21 D20 D19 D18 D17 D16 D15 D14 D13

Using Truncation

8-Bit Data Word

D21 D20 D19 D18 D17 D16 D15 D14

Using Truncation

Output Scaling

D_x[9:1]

A

9 Bit ADDER

PCM

B

CARRY

SUM

Sample updated every 16

μS

9

9

9

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q

D

FF

CLK

Q

Q