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MMA16XXKW Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc |
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MMA16XXKW Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc |
29 / 45 page ![]() Sensors Freescale Semiconductor, Inc. 29 MMA16xxKW 4 DSI Protocol Layer 4.1 Communication Interface Overview The device is compatible with the DSI Bus Standard V2.5. 4.1.1 DSI Physical Layer Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer. 4.1.2 DSI Data Link Layer Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe the DSI data link layer features supported. 4.2 DSI Protocol 4.2.1 DSI Bus Commands DSI Bus Commands are summarized in Table 11. The device supports only the command formats specified in Section 4.2.1. The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is received, the device will not respond. Following all messages, the device requires a minimum inter-frame separation (tIFS). As long as the minimum inter-frame sep- aration times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will be ready for the next message. The device will respond as appropriate during the subsequent DSI transfer. Exactly one response is attempted. Table 11. DSI Bus Command Summary Command Command Format Data C3 C2 C1 C0 Hex Description D7 D6 D5 D4 D3 D2 D1 D0 0000 $0 Initialization Standard Long Only NV BS Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] 0001 $1 Request Status Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 0010 $2 Read Acceleration Data Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 0011 $3 Not Implemented Not Implemented Not Implemented 0100 $4 Request ID Information Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 0101 $5 Not Implemented Not Implemented Not Implemented 0110 $6 Not Implemented Not Implemented Not Implemented 0111 $7 Clear Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 1000 $8 Not Implemented Not Implemented Not Implemented 1001 $9 Read Write NVM Standard/Enhanced L WA[3] WA[2] WA[1] WA[0] RD[3] RD[2] RD[1] RD[0] 1010 $A Format Control Standard/Enhanced L R/W FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] 1011 $B Read Register Data Standard/Enhanced L 0 0 0 0 RA[3] RA[2] RA[1] RA[0] 1100 $C Disable Self-Test Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 1101 $D Activate Self-Test Standard/Enhanced L/S ⎯⎯⎯⎯⎯⎯⎯⎯ 1110 $E Not Implemented Not Implemented Not Implemented 1111 $F Reverse Initialization Not Implemented Not Implemented |
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