Sensors

32

Freescale Semiconductor, Inc.

MMA16xxKW

4.2.1.2

Request Status Command

The Request Status command is supported in the following command formats:

• Standard Long Command

• Standard Short Command

• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)

• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)

The device ignores the Request Status command if the DSI device address is set to the DSI Global Device Address of ‘0000’.

The data bits D[7:0] in the command are only used in the CRC calculation.

Table 16. Request Status Command

Data

Address

Command

CRC

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

C[3]

C[2]

C[1]

C[0]

⎯

⎯

⎯

⎯

⎯

⎯

⎯

⎯

A[3]

A[2]

A[1]

A[0]

0001

0 to 8 bits

Table 17. Request Status Command Bit Definitions

Bit Field

Definition

C[3:0]

Request Status Command = ‘0001’

A[3:0]

DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the

command is ignored.

D[7:0]

Used for CRC calculation only

Table 18. Short Response - Request Status Command

Response

CRC

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

0

0

0

0

0

0

0NV

U

ST

BS

AT[1]

AT[0]

S

0

0 to 8 bits

Table 19. Long Response - Request Status Command

Data

CRC

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

0000

NV

U

ST

BS

AT[1]

AT[0]

S

0

0 to 8 bits

Table 20. Request Status Response Bit Definitions

Bit Field

Definition

S

This bit indicates whether the device has detected an internal device error.

1 - Internal Error detected.

0 - No Internal Error detected

Reference Table 59 for conditions that set the S bit.

AT[1:0]

Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)

BS

Bus Switch state. This bit controls the state of the bus switch:

1 - Close the bus switch

0 - Do not close the bus switch

ST

This bit indicates whether internal self-test circuitry is active

1 - Self-Test active

0 - Self-Test disabled

U

This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.

NV

NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.

1 - OTP programming Enabled

0 - OTP programming Disabled

A[3:0]

DSI device address. This field contains the device address.

Shaded bits are transmitted to meet the response message length of the received message