Sensors

Freescale Semiconductor, Inc.

37

MMA16xxKW

4.2.1.10

Write NVM Command

The Write NVM command is supported in the following command formats:

• Standard Long Command

• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)

The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the

DSI Global Device Address of ‘0000’.

The Write NVM command uses the nibble address definitions in Table 2 and summarized in Table 39.

Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization Command (reference Section 4.2.1.1). If the

NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of

RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to

change the Device Address, the new Device Address is returned.

the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back

being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must

accommodate this timing.

Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a

change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected

if the LOCK_U bit is active (reference Section 3.2.2).

Table 34. Write NVM Command

Data

Address

Command

CRC

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

C[3]

C[2]

C[1]

C[0]

WA[3]

WA[2]

WA[1]

WA[0]

RD[3]

RD[2]

RD[1]

RD[0]

A[3]

A[2]

A[1]

A[0]

1001

0 to 8 bits

Table 35. Write NVM Command Bit Definitions

Bit Field

Definition

C[3:0]

Write NVM Command = ‘1001’

A[3:0]

DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is

ignored.

RD[3:0]

RD[3:0] contains the data to be written to the OTP location addressed by WA[3:0] when the NV bit is set.

WA[3:0]

WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.

Table 36. Long Response - Write NVM Command (NV = 1)

Data

CRC

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

WA[3]

WA[2]

WA[1]

WA[0]

1

1

Bnk[1]

Bnk[0]

RD[3]

RD[2]

RD[1]

RD[0]

0 to 8 bits

Table 37. Long Response - Write NVM Command (NV = 0)

Data

CRC

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

00001111

A[3]

A[2]

A[1]

A[0]

0 to 8 bits

Table 38. Write NVM Response Bit Definitions

Bit Field

Definition

Bnk[1:0]

These bits provide the bank address selected in the Initialization command.

A[3:0]

DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the command is

ignored.

RD[3:0]

RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write.

WA[3:0]

WA[3:0] contains the nibble address of the OTP register to be written to when the NV bit is set.