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MMA16XXKW Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc |
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MMA16XXKW Datasheet(HTML) 38 Page - Freescale Semiconductor, Inc |
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38 / 45 page  Sensors 38 Freescale Semiconductor, Inc. MMA16xxKW Table 39. OTP Register Nibble Address Assignments Bank Address Register Address (Nibble) Register Description Bnk[1] Bnk[0] WA[3] WA[2] WA[1] WA[0] x x 0000 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] x x 0001 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] x x 0010 x x 0011 x x 0100 x x 0101 0 00110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 00111 DEVCFG2[7] Only RD[3] is written to the LOCK_U bit 0 01000 TYPE[7:6] Only RD[3:2] is written to LPF[1:0] 0 01001 DEVCFG[3:0] RD[3] is written to DEVCFG[3] - UNUSED, RD[2:0] is written to CRC_U[2:0] 0 01010 DEVCFG[7:4] RD[3] is written to the DEVID bit, RD[2:0] is written to DEVCFG[6:4] - UNUSED 0 01011 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 01100 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 01101 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 01110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 01111 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 0 10110 DEVCFG1[3:0] RD[3:2] is written to UD00[1:0], RD[1:0] is written to AT[1:0] 0 10111 DEVCFG2[3:0] RD[3:0] is written to ADDR[3:0] 0 11000 UD01[3:0] RD[3:0] is written to UD01[3:0] 0 11001 UD02[3:0] RD[3:0] is written to UD02[3:0] 0 11010 UD03[3:0] RD[3:0] is written to UD03[3:0] 0 11011 UD04[3:0] RD[3:0] is written to UD04[3:0] 0 11100 UD05[3:0] RD[3:0] is written to UD05[3:0] 0 11101 UD06[3:0] RD[3:0] is written to UD06[3:0] 0 11110 UD07[3:0] RD[3:0] is written to UD07[3:0] 0 11111 UD08[3:0] RD[3:0] is written to UD08[3:0] 1 00110 DEVCFG1[7:4] RD[3:0] is written to UD00[5:2] 1 00111 DEVCFG2[5] Only RD[1] is written to the PCM bit 1 01000 UD01[7:4] RD[3:0] is written to UD01[7:4] 1 01001 UD02[7:4] RD[3:0] is written to UD02[7:4] 1 01010 UD03[7:4] RD[3:0] is written to UD03[7:4] 1 01011 UD04[7:4] RD[3:0] is written to UD04[7:4] 1 01100 UD05[7:4] RD[3:0] is written to UD05[7:4] 1 01101 UD06[7:4] RD[3:0] is written to UD06[7:4] 1 01110 UD07[7:4] RD[3:0] is written to UD07[7:4] 1 01111 UD08[7:4] RD[3:0] is written to UD08[7:4] 1 10110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 10111 DEVCFG2[6] Only RD[2] is written to the DEVCFG2[6] bit (UNUSED) 1 11000 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11001 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11010 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11011 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11100 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11101 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0] 1 11111 DEVCFG2[4] Only RD[0] is written to DEVCFG2[4] |
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