Sensors

Freescale Semiconductor, Inc.

41

MMA16xxKW

4.2.1.13

Disable Self-Test Command

The Disable Self-Test command is supported in the following command formats:

• Standard Long Command

• Standard Short Command

• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)

• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)

The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-Test command

with the DSI Global Address of ‘0000’, but does not provide a response.

The Disable Self-Test Command removes the voltage from the self-test plate of the transducer which results in the acceleration

A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout

is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:

• HCAP under-voltage

• A Clear command is received

• Internal regulator under-voltage resulting in a reset.

• A Frame Timeout resulting in a reset.

Table 49. Disable Self-Test Command

Data

Address

Command

CRC

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

C[3]

C[2]

C[1]

C[0]

⎯

⎯

⎯

⎯

⎯

⎯

⎯

⎯

A[3]

A[2]

A[1]

A[0]

1100

0 to 8 bits

Table 50. Disable Self-Test Command Bit Definitions

Bit Field

Definition

C[3:0]

Disable Self-Test Command = ‘1100’

A[3:0]

DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the

command is ignored.

D[7:0]

Used for CRC calculation only

Table 51. Short Response - Disable Self-Test Command

Response

CRC

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

0

0

0

0

0

0

0NV

U

ST

BS

AT[1]

AT[0]

S

0

0 to 8 bits

Table 52. Long Response - Disable Self-Test Command

Data

CRC

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

0000

NV

U

ST

BS

AT[1]

AT[0]

S

0

0 to 8 bits

Table 53. Disable Self-Test Response Bit Definitions

Bit Field

Definition

S

This bit indicates whether the device has detected an internal device error.

1 - Internal Error detected.

0 - No Internal Error detected

Reference Table 59 for conditions that set the S bit.

AT[1:0]

Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)

BS

Bus Switch state. This bit controls the state of the bus switch:

1 - Close the bus switch

0 - Do not close the bus switch

ST

This bit indicates whether internal self-test circuitry is active

1 - Self-Test active

0 - Self-Test disabled

U

This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.

NV

NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.

1 - OTP programming Enabled

0 - OTP programming Disabled

A[3:0]

DSI device address. This field contains the device address.