Sensors

42

Freescale Semiconductor, Inc.

MMA16xxKW

4.2.1.14

Enable Self-Test Command

The Enable Self-Test command is supported in the following command formats:

• Standard Long Command

• Standard Short Command

• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)

• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)

The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command

when it is sent to the DSI Global Address of ‘0000’.

The Enable Self-Test Command applies a voltage to the self-test plate of the transducer which results in a delta in the accel-

eration output value of

command is received.

Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal

self-test circuitry remains disabled, and the ST bit is cleared in the response. Self-Test locking is described in Section 4.2.1.13.

Table 54. Enable Self-Test Command

Data

Address

Command

CRC

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

C[3]

C[2]

C[1]

C[0]

⎯

⎯

⎯

⎯

⎯

⎯

⎯

⎯

A[3]

A[2]

A[1]

A[0]

1101

4 bits

Table 55. Enable Self-Test Command Bit Definitions

Bit Field

Definition

C[3:0]

Enable Self-Test Command = ‘1101’

A[3:0]

DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the

command is ignored.

D[7:0]

Used for CRC calculation only

Table 56. Short Response - Enable Self-Test Command

Response

CRC

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

0

0

0

0

0

0

0NV

U

ST

BS

AT[1]

AT[0]

S

0

4 bits

Table 57. Long Response - Enable Self-Test Command

Data

CRC

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

A[3]

A[2]

A[1]

A[0]

0000

NV

U

ST

BS

AT[1]

AT[0]

S

0

4 bits

Table 58. Enable Self-Test Response Bit Definitions

Bit Field

Definition

S

This bit indicates whether the device has detected an internal device error.

1 - Internal Error detected.

0 - No Internal Error detected

Reference Table 59 for conditions that set the S bit.

AT[1:0]

Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)

BS

Bus Switch state. This bit controls the state of the bus switch:

1 - Close the bus switch

0 - Do not close the bus switch

ST

This bit indicates whether internal self-test circuitry is active

1 - Self-Test active

0 - Self-Test disabled

U

This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.

NV

NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.

1 - OTP programming Enabled

0 - OTP programming Disabled

A[3:0]

DSI device address. This field contains the device address.