Sensors

16

Freescale Semiconductor, Inc.

MMA16xxKW

3.1.5

Device Configuration 2 Register (DEVCFG2)

Device configuration register 2 is a user programmable OTP register which contains device configuration information. This

register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programma-

ble OTP array.

3.1.5.1

User Configuration Lock Bit (LOCK_U, DEVCFG2[7])

The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active.

Reference Section 3.2.2 for details regarding the LOCK_U bit and CRC verification.

3.1.5.2

PCM Bit (DEVCFG2[5])

The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code

Modulated signal proportional to the acceleration response. Reference Section 3.5.3.6 for more information regarding the PCM

output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.

3.1.5.3

Device Address (ADDR[3:0], DEVCFG2[3:0])

The Device Address bits define the preprogrammed DSI Bus device address. If the Device Address bits are programmed to

‘0000’, there is not preprogrammed address, and the address must be assigned via the Initialization DSI command. Reference

Section 4.2.1.1 for more details regarding the Initialization DSI command. These bits can be factory or user programmed.

3.1.6

User Data Registers (UDx)

The User Data Registers are user programmable OTP register which can be programmed with user or assembly specific in-

formation. These registers have no impact on the device performance, but are included in the user register CRC check. Refer to

Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed.

Table 6. Device Control Register

Location

Bit

RA[3:0]

Register

WA[3:0]

7

6

5

4

WA[3:0]

3

2

1

0

$07

DEVCFG2

Bnk0 $07

Bnk2 $07

Bnk3 $07

Bnk3 $0F

LOCK_U

UNUSED

PCM

RESERVED

Bnk1 $07

ADDR[3]

ADDR[2]

ADDR[1]

ADDR[0]

Factory Default

0000

0000

Location

Bit

RA[3:0]

Register

WA[3:0]

7

6

5

4

WA[3:0]

3

2

1

0

$08

UD01

Bnk2 $08

UD01[7]

UD01[6]

UD01[5]

UD01[4]

Bnk1 $08

UD01[3]

UD01[2]

UD01[1]

UD01[0]

$09

UD02

Bnk2 $09

UD02[7]

UD02[6]

UD02[5]

UD02[4]

Bnk1 $09

UD02[3]

UD02[2]

UD02[1]

UD02[0]

$0A

UD03

Bnk2 $0A

UD03[7]

UD03[6]

UD03[5]

UD03[4]

Bnk1 $0A

UD03[3]

UD03[2]

UD03[1]

UD03[0]

$0B

UD04

Bnk2 $0B

UD04[7]

UD04[6]

UD04[5]

UD04[4]

Bnk1 $0B

UD04[3]

UD04[2]

UD04[1]

UD04[0]

$0C

UD05

Bnk2 $0C

UD05[7]

UD05[6]

UD05[5]

UD05[4]

Bnk1 $0C

UD05[3]

UD05[2]

UD05[1]

UD05[0]

$0D

UD06

Bnk2 $0D

UD06[7]

UD06[6]

UD06[5]

UD06[4]

Bnk1 $0D

UD06[3]

UD06[2]

UD06[1]

UD06[0]

$0E

UD07

Bnk2 $0E

UD07[7]

UD07[6]

UD07[5]

UD07[4]

Bnk1 $0E

UD07[3]

UD07[2]

UD07[1]

UD07[0]

$0F

UD08

Bnk2 $0F

UD08[7]

UD08[6]

UD08[5]

UD08[4]

Bnk1 $0F

UD08[3]

UD08[2]

UD08[1]

UD08[0]

Factory Default

0000

0000