Sensors

Freescale Semiconductor, Inc.

17

MMA16xxKW

3.2

OTP Array Lock and CRC Verification

3.2.1

Factory Programmed OTP Array Lock and CRC Verification

The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the

Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which

the internal lock bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.

The Factory programmed OTP array is locked by Freescale and will always be active after POR. The CRC is continuously

calculated on the factory programmed OTP array, which includes the registers listed below:

Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification

CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as spec-

ified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not

the fuse array values.

3.2.2

User Programmable OTP Array Lock and CRC Verification

The User Programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only

when the User Programmable OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout

in which the LOCK_U bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.

Once the LOCK_U bit is active, the CRC is continuously calculated on the user programmable OTP Array, which includes the

registers listed below:

Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification

programmed CRC, CRC_U[2:0], which is also included in the user programmable array. If a CRC mismatch is detected, an in-

ternal data error is set, and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed

on the memory registers which hold a copy of the fuse array values, not the fuse array values. Writes to the User Programmable

OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regard-

less of the state of the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active.

Factory Lock Bit Value in Fuse Array

Lock Bit Value in Mirror Register

After Automatic Readout

Lock Bit Active?

CRC Verification

Enabled?

0

N/A

NO

NO

1

0NO

NO

1

1

YES

YES

Register Name

Register Addresses

Included in Factory CRC?

Serial Number Registers

SN0, SN1, SN2, SN3

Yes

Type Register

TYPE[5:0]

Yes

Factory Programmable Device Configuration

Bits

Internal Register Map

Yes

Factory OTP Array CRC

CRC_F[2:0]

No

Factory OTP Array Lock Bit

LOCK_F

No

Factory Lock Bit Value in Fuse Array

Lock Bit Value in Mirror Register

After Automatic Readout

Lock Bit Active?

CRC Verification

Enabled?

0

N/A

NO

NO

1

0NO

NO

1

1

YES

YES

Register Name

Register Addresses

Included in User CRC?

Type Register

TYPE[7:6]

Yes

Device ID Bit

DEVCFG[7]: DEVID

Yes

User Data Register 0

DEVCFG1[7:2]: UD00[5:0]

Yes

Attribute Bits

DEVCFG1[1:0]: AT_OTP[1:0]

Yes

PCM Bit

DEVCFG2[5]: PCM

Yes

RESERVED Bit

DEVCFG2[4]

Yes

Device Address

DEVCFG2[3:0]: ADDR[3:0]

Yes

User Data Registers 1 - 8

UD01 - UD08

Yes

User Programmable OTP Array CRC

DEVCFG[2:0]: CRC_U[2:0]

No

User Programmable OTP Array Lock Bit

DEVCFG2[7]: LOCK_U

No