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MMA16XXKW Datasheet(PDF) 19 Page - Freescale Semiconductor, Inc |
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MMA16XXKW Datasheet(HTML) 19 Page - Freescale Semiconductor, Inc |
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19 / 45 page  Sensors Freescale Semiconductor, Inc. 19 MMA16xxKW 3.3.3 VREG, and VREGA Under-Voltage Monitor The device includes a circuit to monitor the internally regulated voltages (VREG and VREGA). If either of the internal regulator voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (tVREG_POR, tVREGA_POR) specified in Section 2.7. 3.3.4 VREG and VREGA Capacitance Monitor A monitor circuit is incorporated to ensure predictable operation if the connection to the external CREG or CREGA capacitor becomes open. At a continuous rate specified in Section 2.7 (tCAPTEST_RATE), both regulators are simultaneously disabled for a short duration (tCAPTEST_TIME). If either of the external capacitors are not present, the associated regulator voltage will fall below the internal reset threshold, forcing a device reset. Figure 10. VREG Capacitor Monitor Figure 11. VREGA Capacitor Monitor 3.4 Internal Oscillator The device includes a factory trimmed oscillator as specified in Section 2.8. CAP_Test VREG Time Capacitor Present VPORVREG_f POR Capacitor Open tCAPTEST_TIME tCAPTEST_RATE CAP_Test VREGA Time Capacitor Present VPORREGA_f POR Capacitor Open tCAPTEST_TIME tCAPTEST_RATE |
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