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FT8010MPX Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FT8010MPX Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 13 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FT8010 • Rev. 1.0.7 3 Pin Configuration Figure 2. MLP Pin Configuration (1) (Top Through View) Figure 3. UMLP Pin Configuration (2) (Top Through View) Note: 1. The DAP may be a no connect or it may be tied to ground. 2. NC = No connect Pin Definitions MLP Pin # UMLP Pin # Name Description 1 10 RST2 Push-Pull Output, Active HIGH 2 1 GND Ground 3 2 /SR1 Secondary Reset Input, Active LOW 4 3 /RST1 Open-Drain Output, Active LOW 5 5 DSR Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or pull-down resistors.) 6 6 TRIG Test Pin, Tied to GND in Normal Use 7 7 /SR0 Primary Reset Input, Active LOW 8 8 VCC Power Supply 4, 9, NC No Connect |
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