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WM8321 Datasheet(PDF) 155 Page - Wolfson Microelectronics plc |
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WM8321 Datasheet(HTML) 155 Page - Wolfson Microelectronics plc |
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155 / 253 page  Production Data WM8321 w PD, February 2012, Rev 4.0 155 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 = No interrupt 1 = Interrupt is asserted 5 RTC_INT 0 Real Time Clock and Crystal Oscillator primary interrupt 0 = No interrupt 1 = Interrupt is asserted 4 OTP_INT 0 OTP Memory primary interrupt 0 = No interrupt 1 = Interrupt is asserted 1 HC_INT 0 High Current primary interrupt 0 = No interrupt 1 = Interrupt is asserted 0 UV_INT 0 Undervoltage primary interrupt 0 = No interrupt 1 = Interrupt is asserted Register 4010h System Interrupts REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R16401 (4011h) Interrupt Status 1 15 PPM_SYSLO_ EINT 0 Power Path SYSLO interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 12 ON_PIN_CINT 0 ON pin interrupt. (Rising and Falling Edge triggered) Note: Cleared when a ‘1’ is written. 11 WDOG_TO_EI NT 0 Watchdog timeout interrupt. (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 8 AUXADC_DAT A_EINT 0 AUXADC Data Ready interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 7 AUXADC_DCO MP4_EINT 0 AUXADC Digital Comparator 4 interrupt (Trigger is controlled by DCMP4_GT) Note: Cleared when a ‘1’ is written. 6 AUXADC_DCO MP3_EINT 0 AUXADC Digital Comparator 3 interrupt (Trigger is controlled by DCMP3_GT) Note: Cleared when a ‘1’ is written. 5 AUXADC_DCO MP2_EINT 0 AUXADC Digital Comparator 2 interrupt (Trigger is controlled by DCMP2_GT) Note: Cleared when a ‘1’ is written. 4 AUXADC_DCO MP1_EINT 0 AUXADC Digital Comparator 1 interrupt (Trigger is controlled by DCMP1_GT) Note: Cleared when a ‘1’ is written. 3 RTC_PER_EIN T 0 RTC Periodic interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. 2 RTC_ALM_EIN T 0 RTC Alarm interrupt (Rising Edge triggered) Note: Cleared when a ‘1’ is written. |
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