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74LS85 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LS85 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS006379 www.fairchildsemi.com August 1986 Revised March 2000 DM74LS85 4-Bit Magnitude Comparator General Description These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded deci- sions about two, 4-bit words (A, B) are made and are exter- nally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B out- puts of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the least- significant bits must have a high-level voltage applied to the A = B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words. Features s Typical power dissipation 52 mW s Typical delay (4-bit words) 24 ns Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Order Number Package Number Package Description DM74LS85M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS85N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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