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IR5001STRPBF Datasheet(PDF) 11 Page - International Rectifier |
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IR5001STRPBF Datasheet(HTML) 11 Page - International Rectifier |
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11 / 12 page  IR5001S & (PbF) 11 www.irf.com In a well - designed Active ORing circuit, the Rds(on) of the Active ORing FET should generate between 50mV to 100mV of (INP – INN) voltage during normal, steady state operation. (The normal operation refers to current flowing from the source to drain of the Active ORing FET, half of the full-load system current flowing through each OR-ed source, at nominal input voltage). Maximum power dissipation under worst-case conditions for the FET should be calculated and verified against the data sheet limits of the selected device. IR5001S Thermal considerations Maximum junction temperature of the IR5001S in an application should not exceed the maximum operating junction temperature, specified at 125°C: Tj = Pdiss * Rtheta j-a + Tamb <= Tj (max), where Rtheta j-a is the thermal resistance from junction to ambient thermal resistance (specified at 128 °C/W), Pdiss is IC power dissipation, and Tamb is operating ambient temperature. The maximum power dissipation can be estimated as follows: Pdiss < (Tj max – Tamb max) / Rtheta j-a Since Tj max= 125 °C, Tamb = 85 °C, and Rtheta j-a = 128 °C/W, the maximum power dissipation allowed is: Pdiss max = (125 – 85) / 128 = 0.3W With proper selection of Icc (as discussed in the Detailed Pin Description), the maximum power dissipation will never be exceeded (Max Icc * Max Vcc = 10mA * 13.9V = 0.14W). Layout Considerations INN and INP should be connected very close to the drain and source terminal of the Active ORing FET. PCB trace between the Vout pin and the gate of the N-FET should also be minimized. A minimum of 0.1uF decoupling capacitor must be connected from Vcc to Gnd of the IR5001S and should be placed as close to the IR5001S as possible. Ground should be connected to the source of N-FET separately from the INP pin. |
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Similar Description - IR5001STRPBF |
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