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C8051F040-GQR Datasheet(PDF) 34 Page - Silicon Laboratories |
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C8051F040-GQR Datasheet(HTML) 34 Page - Silicon Laboratories |
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34 / 328 page  C8051F040/1/2/3/4/5/6/7 34 Rev. 1.5 1.10. Comparators and DACs Each C8051F040/1/2/3 MCU has two 12-bit DACs, and all C8051F04x devices have three comparators on chip. The MCU data and control interface to each comparator and DAC is via the Special Function Regis- ters. The MCU can place any DAC or comparator in low power shutdown mode. The comparators have software programmable hysteresis and response time. Each comparator can gen- erate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the MCU from sleep mode. The comparators' output state can also be polled in software. The comparator out- puts can be programmed to appear on the Port I/O pins via the Crossbar. The DACs are voltage output mode and include a flexible output scheduling mechanism. This scheduling mechanism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage reference is supplied via the dedicated VREFD input pin on C8051F040/2 devices or via the internal voltage reference on C8051F041/3 devices. The DACs are especially useful as references for the comparators or offsets for the differential inputs of the ADC. Figure 1.14. Comparator and DAC Diagram + - CPn+ CPn- DAC0 DAC1 VR E F VR E F CIP -51 and Interrupt H andler CPn D AC 0 D AC 1 C Pn O utput (Port I/O ) SFR's (D ata and Cntrl) C R O SS BAR 3 C om parators C om parator inputs Port 2.[7:2] (C 8051F040/1/2/3 only) (C 8051F040/1/2/3 only) |
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