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DSPIC33FJ12MC201TESS Datasheet(PDF) 108 Page - Microchip Technology |
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DSPIC33FJ12MC201TESS Datasheet(HTML) 108 Page - Microchip Technology |
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108 / 304 page  dsPIC33FJ12MC201/202 DS70265E-page 108 © 2007-2011 Microchip Technology Inc. bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) Note 1: Writes to this register require an unlock sequence. Refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip web site) for details. 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). |
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