DSPIC33FJ12MC201TESS datasheet(120/304 Pages) MICROCHIP

120 / 304 page

dsPIC33FJ12MC201/202

DS70265E-page 120

10.1.1

OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT, and TRIS registers for

data control, some port pins can also be individually

configured for either digital or open-drain output. This

is controlled by the Open-Drain Control register,

ODCx, associated with each port. Setting any of the

bits configures the corresponding pin to act as an

open-drain output.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any 5V-tolerant

pins by using external pull-up resistors. The maximum

open-drain voltage allowed is the same as the

maximum VIH specification.

See “Pin Diagrams” for the available pins and their

functionality.

10.2

Configuring Analog Port Pins

The AD1PCFG and TRIS registers control the opera-

tion of the analog-to-digital (A/D) port pins. The port

pins that are to function as analog inputs must have

their corresponding TRIS bit set (input). If the TRIS bit

is cleared (output), the digital output level (VOH or VOL)

will be converted.

The AD1PCFGL register has a default value of 0x0000;

therefore, all pins that share ANx functions are analog

(not digital) by default.

When the PORT register is read, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

10.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be an NOP. An demonstration is shown in

Example 10-1.

10.3

Input Change Notification

The input change notification function of the I/O ports

allows the dsPIC33FJ12MC201/202 devices to gener-

ate interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature

can detect input change-of-states even in Sleep mode,

when the clocks are disabled. Depending on the device

pin count, up to 21 external signals (CNx pin) can be

selected (enabled) for generating an interrupt request

on a change-of-state.

Four control registers are associated with the CN mod-

ule. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source connected to the

pin, and eliminate the need for external resistors when

push-button or keypad devices are connected. The

pull-ups are enabled separately using the CNPU1 and

CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

Note:

Pull-ups on change notification pins

should always be disabled when the port

pin is configured as a digital output.

MOV

0xFF00, W0

; Configure PORTB<15:8> as inputs

MOV

W0, TRISBB

; and PORTB<7:0> as outputs

NOP

; Delay 1 cycle

btss

PORTB, #13

; Next Instruction

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