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PIC18F2525 Datasheet(PDF) 27 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 27 Page - Microchip Technology |
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27 / 412 page  © 2008 Microchip Technology Inc. DS39626E-page 25 PIC18F2525/2620/4525/4620 2.4 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The actual oscillator frequency is a function of several factors: • supply voltage • values of the external resistor (REXT) and capacitor (CEXT) • operating temperature Given the same device, operating voltage and tempera- ture and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: • normal manufacturing variation • difference in lead frame capacitance between package types (especially for low CEXT values) • variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected. FIGURE 2-5: RC OSCILLATOR MODE The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-6: RCIO OSCILLATOR MODE 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 HSPLL OSCILLATOR MODE The HSPLL mode makes use of the HS Oscillator mode for frequencies up to 10 MHz. A PLL then multi- plies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 Configuration bits are programmed for HSPLL mode (= 0110). FIGURE 2-7: PLL BLOCK DIAGRAM (HS MODE) 2.5.2 PLL AND INTOSC The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 “PLL in INTOSC Modes”. OSC2/CLKO CEXT REXT PIC18FXXXX OSC1 FOSC/4 Internal Clock VDD VSS Recommended values: 3 k Ω ≤ REXT ≤ 100 kΩ CEXT > 20 pF CEXT REXT PIC18FXXXX OSC1 Internal Clock VDD VSS Recommended values: 3 k Ω ≤ REXT ≤ 100 kΩ CEXT > 20 pF I/O (OSC2) RA6 VCO Loop Filter Crystal Osc OSC2 OSC1 PLL Enable FIN FOUT SYSCLK Phase Comparator HS Oscillator Enable ÷4 (from Configuration Register 1H) HS Mode |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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