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PIC18F2525 Datasheet(PDF) 37 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 37 Page - Microchip Technology |
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37 / 412 page  © 2008 Microchip Technology Inc. DS39626E-page 35 PIC18F2525/2620/4525/4620 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to ‘1’. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compat- ibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Q4 Q3 Q2 OSC1 Peripheral Program Q1 T1OSI Q1 Counter Clock CPU Clock PC + 2 PC 123 n-1 n Clock Transition(1) Q4 Q3 Q2 Q1 Q3 Q2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. Q1 Q3 Q4 OSC1 Peripheral Program PC T1OSI PLL Clock Q1 PC + 4 Q2 Output Q3 Q4 Q1 CPU Clock PC + 2 Clock Counter Q2 Q2 Q3 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. SCS1:SCS0 bits Changed TPLL(1) 12 n-1 n Clock OSTS bit Set Transition(2) TOST(1) Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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