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PIC18F2525 Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 412 page  © 2008 Microchip Technology Inc. DS39626E-page 37 PIC18F2525/2620/4525/4620 3.3 Sleep Mode The power-managed Sleep mode in the PIC18F2525/ 2620/4525/4620 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 23.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 26-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time- out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q4 Q3 Q2 OSC1 Peripheral Sleep Program Q1 Q1 Counter Clock CPU Clock PC + 2 PC Q3 Q4 Q1 Q2 OSC1 Peripheral Program PC PLL Clock Q3 Q4 Output CPU Clock Q1 Q2 Q3 Q4 Q1 Q2 Clock Counter PC + 6 PC + 4 Q1 Q2 Q3 Q4 Wake Event Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. TOST(1) TPLL(1) OSTS bit Set PC + 2 |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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