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PIC18F2525 Datasheet(PDF) 67 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 67 Page - Microchip Technology |
67 / 412 page © 2008 Microchip Technology Inc. DS39626E-page 65 PIC18F2525/2620/4525/4620 SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 51, 206 SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 51, 206 RCREG EUSART Receive Register 0000 0000 51, 213 TXREG EUSART Transmit Register 0000 0000 51, 211 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 202 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 203 EEADRH — — — — — — EEPROM Addr Register High ---- --00 51, 73 EEADR EEPROM Address Register 0000 0000 51, 80, 73 EEDATA EEPROM Data Register 0000 0000 51, 80, 73 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 80, 73 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 81, 74 IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 119 PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 115 PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 117 IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 118 PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 114 PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 116 OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 27, 52 TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 104 TRISD(2) PORTD Data Direction Control Register 1111 1111 52, 100 TRISC PORTC Data Direction Control Register 1111 1111 52, 97 TRISB PORTB Data Direction Control Register 1111 1111 52, 94 TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 52, 91 LATE(2) — — — — — PORTE Data Latch Register (Read and Write to Data Latch) ---- -xxx 52, 103 LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 100 LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 97 LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 94 LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 91 PORTE — — — —RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 52, 103 PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 100 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 97 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 94 PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 91 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2525/2620/4525/4620) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”. 2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices; individual unimplemented bits should be interpreted as ‘-’. 3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes”. 4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is read-only. 5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 6: Bit 7 and bit 6 are cleared by user software or by a POR. |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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