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PIC18F2525 Datasheet(PDF) 82 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 82 Page - Microchip Technology |
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82 / 412 page  PIC18F2525/2620/4525/4620 DS39626E-page 80 © 2008 Microchip Technology Inc. FIGURE 7-2: TABLE WRITE OPERATION 7.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • EECON1 register • EECON2 register • TABLAT register • TBLPTR registers 7.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 23.0 “Special Features of the CPU”). When clear, memory selection access is determined by EEPGD. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Table Pointer(1) Table Latch (8-bit) TBLPTRH TBLPTRL TABLAT Program Memory (TBLPTR) TBLPTRU Instruction: TBLWT* Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. Holding Registers Program Memory Note: During normal operation, the WRERR may read as ‘1’. This can indicate that a write operation was prematurely termi- nated by a Reset, or a write operation was attempted improperly. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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