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PIC18F2525 Datasheet(PDF) 18 Page - Microchip Technology |
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PIC18F2525 Datasheet(HTML) 18 Page - Microchip Technology |
18 / 412 page PIC18F2525/2620/4525/4620 DS39626E-page 16 © 2008 Microchip Technology Inc. TABLE 1-3: PIC18F4525/4620 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description PDIP QFN TQFP MCLR/VPP/RE3 MCLR VPP RE3 118 18 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 13 32 30 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; analog otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 14 33 31 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared. 3: For the QFN package, it is recommended that the bottom pad be connected to VSS. |
Similar Part No. - PIC18F2525_08 |
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Similar Description - PIC18F2525_08 |
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