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ICS874001AGI-05LF Datasheet(PDF) 6 Page - Integrated Device Technology |
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ICS874001AGI-05LF Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 18 page ICS874001AGI-05 REVISION A JANUARY 14, 2011 6 ©2011 Integrated Device Technology, Inc. ICS74001I-05 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 4: Guaranteed only when input clock source is PCI Express and PCI Express Gen 2 compliant. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 98 640 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 50 ps Tj (PCIe Gen 1) Phase Jitter Peak-to-Peak; NOTE 2, 4 100MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 16.14 ps 125MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 15.64 ps 250MHz output, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 13.16 ps 500MHz, (1.2MHz –21.9MHz), Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12.17 ps TREFCLK_HF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 3, 4 100MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.4 ps 125MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.39 ps 250MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.18 ps 500MHz output, High Band: 1.5MHz - Nyquist (clock frequency/2) 1.11 ps TREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS; NOTE 3, 4 100MHz output, Low Band: 10kHz - 1.5MHz 0.33 ps 125MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 250MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps 500MHz output, Low Band: 10kHz - 1.5MHz 0.22 ps tR / tF Output Rise/Fall Time 20% to 80% 200 600 ps odc Output Duty Cycle F_SEL[10] ≠ 11 48 52 % F_SEL[10] = 11 42 58 % |
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