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TAS5760L Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5760L Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 57 page  ANA_REG SFT_CLIP AVDD VCOM ANA_REF SPK_FAULT FREQ/SDA SPK_SD PBTL/SCL DVDD GVDD_REG GGND BSTRPA+ SPK_OUTA+ PVDD PGND SPK_OUTA- BSTRPA- BSTRPB- SPK_OUTB- SPK_GAIN0 SPK_GAIN1 SPK_SLEEP/ADR SCLK PGND PVDD SPK_OUTB+ DGND BSTRPB+ LRCK MCLK SDIN PowerPAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TAS5760L www.ti.com SLOS782 – JULY 2013 TSSOP PACKAGE DAP-32 (TOP VIEW) Pin Descriptions TAS5760L Internal No. Type(1) Description Termination Name AVDD 1 P - Power supply for internal analog circuitry Connection point for internal reference used by ANA_REG and VCOM filter ANA_REF 5 P - capacitors Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a ANA_REG 3 P - connection point for filtering capacitors for this supply and must not be used to power any external circuitry) Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a BSTRPA- 25 P - power supply for the high-side gate drive for SPK_OUTA- Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a BSTRPA+ 30 P - power supply for the high-side gate drive for SPK_OUTA Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a BSTRPB- 24 P - power supply for the high-side gate drive for SPK_OUTB- Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a BSTRPB+ 19 P - power supply for the high-side gate drive for SPK_OUTB+ Ground for digital circuitry (NOTE: This terminal should be connected to the system DGND 18 G - ground) DVDD 10 P - Power supply for the internal digital circuitry Weak Pull- Dual function terminal that functions as an I²C data input terminal in I²C Control FREQ/SDA 8 DI Down Mode or as a Frequency Select terminal when in Hardware Control Mode. Ground for gate drive circuitry (this terminal should be connected to the system GGND 31 G - ground) Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a GVDD_REG 32 P - connection point for filtering capacitors for this supply and must not be used to power any external circuitry) Weak Pull- Word select clock for the digital signal that is active on the serial port's input data LRCK 17 DI Down line Weak Pull- Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio MCLK 14 DI Down Port clocking Dual function terminal that functions as an I²C clock input terminal in I²C Control Weak Pull- PBTL/SCL 9 DI Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load Down (PBTL) mode when in Hardware Control Mode (1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0V) Copyright © 2013, Texas Instruments Incorporated 5 Product Folder Links: TAS5760L |
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