H5PS1G83JFR datasheet(23/62 Pages) HYNIX

Part #	H5PS1G83JFR

Description	1Gb DDR2 SDRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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23 / 62 page

Rev. 1.7 / Apr. 2012

23

H5PS1G83JFR Series

(DDR2-667 and DDR2-800)

Parameter

Symbol

DDR2-667

DDR2-800

Unit

Note

min

max

min

max

DQ output access time from CK/CK

tAC

-450

+450

-400

+400

ps

40

DQS output access time from CK/CK

tDQSCK

-400

+400

-350

+350

ps

40

CK HIGH pulse width

tCH(avg)

0.48

0.52

0.48

0.52

tCK(avg)

35,36

CK LOW pulse width

tCL(avg)

0.48

0.52

0.48

0.52

tCK(avg)

35,36

CK half period

tHP

min(tCL(abs),

tCH(abs))

-

min(tCL(abs),

tCH(abs))

-

ps

37

Clock cycle time, CL=x

tCK(avg)

3000

8000

2500

8000

ps

35,36

DQ and DM input setup time

tDS(base)

100

-

50

-

ps

6,7,8,20,28,31

DQ and DM input hold time

tDH(base)

175

-

125

-

ps

6,7,8,21,28,31

Control & Address input pulse width for each input

tIPW

0.6

-

0.6

-

tCK(avg)

DQ and DM input pulse width for each input

tDIPW

0.35

-

0.35

-

tCK(avg)

Data-out high-impedance time from CK/CK

tHZ

-

tAC max

-

tAC max

ps

18,40

DQS low-impedance time from CK/CK

tLZ(DQS)

tAC min

tAC max

tAC min

tAC max

ps

18,40

DQ low-impedance time from CK/CK

tLZ(DQ)

2*tAC min

tAC max

2*tAC min

tAC max

ps

18,40

DQS-DQ skew for DQS and associated DQ signals

tDQSQ

-

240

-200

ps

13

DQ hold skew factor

tQHS

-

340

-300

ps

38

DQ/DQS output hold time from DQS

tQH

tHP - tQHS

-

tHP - tQHS

-

ps

39

First DQS latching transition to associated clock

edge

tDQSS

- 0.25

+ 0.25

- 0.25

+ 0.25

tCK(avg)

30

DQS input HIGH pulse width

tDQSH

0.35

-

0.35

-

tCK(avg)

DQS input LOW pulse width

tDQSL

0.35

-

0.35

-

tCK(avg)

DQS falling edge to CK setup time

tDSS

0.2

-

0.2

-

tCK(avg)

30

DQS falling edge hold time from CK

tDSH

0.2

-

0.2

-

tCK(avg)

30

Mode register set command cycle time

tMRD

2

-

2

-

tCK(avg)

Write preamble

tWPRE

0.35

-

0.35

-

tCK(avg)

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK(avg)

10

Address and control input setup time

tIS(base)

200

-175

-

ps

5,7,9,22,29

Address and control input hold time

tIH(base)

275

-250

-

ps

5,7,9,23,29

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK(avg)

19,41

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK(avg)

19,42

Activate to precharge command

tRAS

45

70000

45

70000

ns

3

Active to active command period for 1KB page size

products (x4, x8)

tRRD

7.5

-7.5

-

ns

4,32

Active to active command period for 2KB page size

products (x16)

tRRD

10

-10

-

ns

4,32

Four Active Window for 1KB page size products

tFAW

37.5

-

35

-

ns

32

Four Active Window for 2KB page size products

tFAW

50

-

45

-

ns

32

CAS to CAS command delay

tCCD

2

nCK

Write recovery time

tWR

15

-15

-

ns

32

Auto precharge write recovery + precharge time

tDAL

WR+tnRP

-

WR+tnRP

-

nCK

33

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