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H5PS1G83JFR Datasheet(PDF) 49 Page - Hynix Semiconductor |
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H5PS1G83JFR Datasheet(HTML) 49 Page - Hynix Semiconductor |
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49 / 62 page  Rev. 1.7 / Apr. 2012 49 Release H5PS1G83JFR Series VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its comple- ment, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differen- tial data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation. 5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. All voltages referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/ supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. tDS tDS tDH tWPRE tWPST tDQSH tDQSL DQS DQS D DMin DQS/ DQ DM tDH Figure -- Data input (write) timing DMin DMin DMin D D D DQS VIH(ac) VIL(ac) VIH(ac) VIL(ac) VIH(dc) VIL(dc) VIH(dc) VIL(dc) tCH tCL CK CK CK/CK DQS/DQS DQ DQS DQS tRPST Q tRPRE tDQSQmax tQH tQH tDQSQmax Figure -- Data output (read) timing Q QQ |
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