H5PS5182GFRS6C datasheet(22/64 Pages) HYNIX

Part #	H5PS5182GFRS6C

Description	512Mb DDR2 SDRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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22 / 64 page

Rev.1.7 / Feb. 2013

22

H5PS5162GFR series

Timing Parameters by Speed Grade

(Refer to notes for information related to this table at the following pages of this table)

Parameter

Symbol

DDR2-400

DDR2-533

Unit Note

min

max

min

max

Clock cycle time, CL=x

tCK

5000

8000

3750

8000

ps

15

CK high-level width

tCH

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.45

0.55

0.45

0.55

tCK

DQ output access time from CK/CK

tAC

-600

+600

-500

+500

ps

DQS output access time from CK/CK

tDQSCK

-500

+500

-450

+450

ps

Write command to DQS associated clock edge WL

RL - 1

tCK

First DQS latching transition to associated

clock edge

tDQSS

-0.25

0.25

-0.25

0.25

tCK

DQS falling edge to CK setup time

tDSS

0.2

-

0.2

-

tCK

DQS falling edge hold time from CK

tDSH

0.2

-

0.2

-

tCK

DQS input high pulse width

tDQSH

0.35

-

0.35

-

tCK

DQS input low pulse width

tDQSL

0.35

-

0.35

-

tCK

Write preamble

tWPRE

0.35

-

0.35

-

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

tCK

10

Address and control input setup time

tIS(base)

350

-

250

-

ps

5,7,9,

22

Address and control input hold time

tIH(base)

475

-

375

-

ps

5,7,9,

23

Control & Address input pulse width for each

input

tIPW

0.6

-0.6

-

tCK

DQ and DM input setup time

(differential strobe)

tDS

(base)

150

-

100

-

ps

6,7,8,

20,28

DQ and DM input hold time

(differential strobe)

tDH

(base)

275

-

225

-

ps

6,7,8,

21,28

DQ and DM input setup time

(single ended strobe)

tDS1

(base)

25

--25

-

ps

6,7,8,

25

DQ and DM input hold time

(single ended strobe)

tDH1

(base)

25

--25

-

ps

6,7,8,

26

DQ and DM input pulse width for each input

tDIPW

0.35

-0.35

-

tCK

DQ output access time from CK/CK

tAC

- 600

+ 600

- 500

+ 500

ps

DQS output access time from CK/CK

tDQSCK

- 500

+ 500

- 450

+ 450

ps

Data-out high-impedance time from CK/CK

tHZ

-

tAC max

-

tAC max

ps

18

DQS low-impedance time from CK/CK

tLZ(DQS)

tAC min

tAC max

tAC min

tAC max

ps

18

DQ low-impedance time from CK/CK

tLZ(DQ)

2*tAC min tAC max

ps

18

DQS-DQ skew for DQS and associated DQ

signals

tDQSQ

-

350

-300

ps

13

CK half period

tHP

min

(tCL,tCH)

-

min

(tCL,tCH)

-

ps

11,12

DQ hold skew factor

tQHS

-

450

-400

ps

12

DQ/DQS output hold time from DQS

tQH

tHP - tQHS

-

tHP - tQHS

-

ps

Read preamble

tRPRE

0.9

1.1

0.9

1.1

tCK

Read postamble

tRPST

0.4

0.6

0.4

0.6

tCK

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H5PS5182GFRS6C Datasheet(PDF) 22 Page - Hynix Semiconductor

H5PS5182GFRS6C Datasheet(HTML) 22 Page - Hynix Semiconductor

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