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H5PS1G63JFRS6C Datasheet(PDF) 26 Page - Hynix Semiconductor |
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H5PS1G63JFRS6C Datasheet(HTML) 26 Page - Hynix Semiconductor |
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26 / 62 page  Rev. 1.7 / Nov. 2011 26 Release H5PS1G63JFR Series 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMR “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its com- plement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMR, the complementary pin, DQS, must be tied exter- nally to VSS through a 20 to 10 K resistor to insure proper operation. 5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. All voltages referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer- ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. tDS tDS tDH tWPRE tWPST tDQSH tDQSL DQS DQS D DMin DQS/ DQ DM tDH Figure -- Data input (write) timing DMin DMin DMin D D D DQS VIH(ac) VIL(ac) VIH(ac) VIL(ac) VIH(dc) VIL(dc) VIH(dc) VIL(dc) tCH tCL CK CK CK/CK DQS/DQS DQ DQS DQS tRPST Q tRPRE tDQSQmax tQH tQH tDQSQmax Figure -- Data output (read) timing Q QQ |
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