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H5PS1G63JFRS6C Datasheet(PDF) 29 Page - Hynix Semiconductor |
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H5PS1G63JFRS6C Datasheet(HTML) 29 Page - Hynix Semiconductor |
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29 / 62 page  Rev. 1.7 / Nov 2011 29 Release H5PS1G63JFR Series If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in table, the derating values may obtained by linear interpola- tion. These values are typically not subject to production test. They are verified by design and characterization. |
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