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H5PS5162GFRS6C Datasheet(PDF) 45 Page - Hynix Semiconductor

Part # H5PS5162GFRS6C
Description  512Mb DDR2 SDRAM
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5PS5162GFRS6C Datasheet(HTML) 45 Page - Hynix Semiconductor

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Rev.1.7 / Feb. 2013
45
H5PS5162GFR series
For purposes of IDD testing, the following parameters are to be utilized
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x16
-DDR2-1066 7-7-7: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D
Speed Bin
(CL-tRCD-tRP)
DDR2-1066
Units
7-7-7
CL(IDD)
7
tCK
tRCD(IDD)
13.125
ns
tRC(IDD)
58.125
ns
tRRD(IDD)-x16
10
ns
tFAW-x16
45
ns
tCK(IDD)
1.875
ns
tRASmin(IDD)
45
ns
tRASmax(IDD)
70000
ns
tRP(IDD)
13.125
ns
tRFC(IDD)-256Mb
75
ns
tRFC(IDD)-512Mb
105
ns
tRFC(IDD)-1Gb
127.5
ns


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