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AM3703CUS Datasheet(PDF) 187 Page - Texas Instruments

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Part # AM3703CUS
Description  Sitara ARM Microprocessors
PDF  280 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3703CUS Datasheet(HTML) 187 Page - Texas Instruments

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LPDDRDevice
RegionshouldencompassallLPDDRcircuitryandvariesdepending
onplacement.Non-LPDDRsignalsshouldnotberoutedonthe
LPDDRsignallayerswithintheLPDDRkeepoutregion.Non-LPDDR
signalsmayberoutedintheregionprovidedtheyareroutedon
layersseparatedfromLPDDRsignallayersbyagroundlayer.No
breaksshouldbeallowedinthereferencegroundlayersinthis
region.Inaddition,the1.8Vpowerplaneshouldcovertheentirekeep
outregion.
AM3715, AM3703
www.ti.com
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
Figure 6-20. LPDDR Keepout Region
6.4.2.4
Net Classes
Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
Table 6-17. Clock Net Class Definitions
CLOCK NET CLASS
PIN NAMES
CK
sdrc_clk/sdrc_nclk
DQS0
sdrc_dqs0
DQS1
sdrc_dqs1
DQS2
sdrc_dqs2
DQS3
sdrc_dqs3
Table 6-18. Signal Net Class Definitions
CLOCK NET CLASS
ASSOCIATED CLOCK NET CLASS
PIN NAMES
sdrc_ba[1:0], sdrc_a[14:0], sdrc_ncs[1:0],
ADDR_CTRL
CK
sdrc_ncas, sdrc_nras, sdrc_nwe,
sdrc_cke[1:0]
DQ0
DQS0
sdrc_d[7:0], sdrc_dm0
DQ1
DQS1
sdrc_d[15:8], sdrc_dm1
DQ2
DQS2
sdrc_d[23:16], sdrc_dm2
DQ3
DQS3
sdrc_d[31:24], sdrc_dm3
6.4.2.5
LPDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-19 shows the specifications for the series terminators.
Copyright
© 2010–2011, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
187
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Product Folder Link(s): AM3715 AM3703



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