AM3703CUS datasheet(195/280 Pages) TI

195 / 280 page

cam_xclki

cam_pclk

cam_vs

cam_hs

cam_d[11:0]

cam_wen

cam_fld

D(0)

D(n–3)

D(n–2)

D(n–1)

D(0)

D(1)

ISP15

ISP16

ISP17

ISP18

ISP19

ISP20

ISP21

ISP22

ISP24

ISP23

ISP25

ISP26

ISP18

SWPS038-050

D(n–1)

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

(1)

The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output,

the signal length can be set.

(2)

The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3)

When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4)

However, it is possible to shift the data to 0, 2, or 4 data internal lanes.

(5)

The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode and cam_d[11:0] in 12-bit mode.

(6)

Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7)

The cam_wen signal can be used as an external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs,

and cam_wen signals are asserted.

(8)

In cam_xclki, i can be equal to a or b. See Table 6-22 for ISP15 and ISP16 parameters.

Figure 6-25. CPI

—12-Bit SYNC Normal Progressive Mode

6.5.1.2.3 CPI

—8-Bit SYNC Packed Progressive Mode

Table 6-28 assumes testing over the recommended operating conditions and electrical characteristic

conditions below (see Figure 6-26).

Table 6-27. CPI Timing Conditions

—8-Bit SYNC Packed Progressive Mode(1)

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

2.5

Input signal fall time

2.5

Output Condition

CLOAD

Output load capacitance

8.6

Timing Requirements and Switching Characteristics

195

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AM3703CUS Datasheet(PDF) 195 Page - Texas Instruments

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