AM3703CUS datasheet(223/280 Pages) TI

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AM3715, AM3703

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SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

6.6.2

Multichannel Serial Port Interface (McSPI)

NOTE

For more information, see Multichannel SPI chapter of the AM/DM37x Multimedia Device

Technical Reference Manual (literature number SPRUGN4).

McSPI allows a duplex, synchronous, serial communication between a local host and SPI compliant

external devices. The following timings are applicable to the different configurations of McSPI in

master/slave mode for any McSPI and any channel (n).

6.6.2.1

McSPI

—Slave Mode

In slave mode, McSPI initiates data transfer on the data lines (mcspix_somi, mcspix_simo) when it

receives an SPI clock (mcspix_clk) from the external SPI master device.

Table 6-75 and Table 6-76 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-44 and Figure 6-45).

Table 6-74. McSPI Timing Conditions

—Slave Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

CLOAD

Output load capacitance(1)

(1) The load setting of the IO buffer: LB0 = 1.

Table 6-75. McSPI Timing Requirements

—Slave Mode(1) (3)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

SS0

1/tc(CLK)

Frequency, mcspix_clk

MHz

SS1

tw(CLK)

Pulse duration, mcspix_clk high or low

0.45*P(2)

0.55*P(2)

0.45*P(2)

0.55*P(2)

SS2

tsu(SIMOV-CLKAE) Setup time, mcspix_simo valid before mcspix_clk

4.2

9.5

active edge

SS3

th(SIMOV-CLKAE)

Hold time, mcspix_simo valid after mcspix_clk active

4.6

9.9

edge

SS4

tsu(CS0V-CLKFE)

Setup time, mcspix_cs0 valid before mcspix_clk first

13.8

28.6

edge

SS5

th(CS0I-CLKLE)

Hold time, mcspix_cs0 invalid after mcspix_clk last

13.8

28.6

edge

(1) In mcspix, x is equal to 1, 2, 3, or 4.

(2) P = mcspix_clk clock period

(3) See Section 4.3.4, Processor Clocks.

Timing Requirements and Switching Characteristics

223

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