DSPIC33FJ12GP201TESLASHML datasheet(147/242 Pages) MICROCHIP

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Preliminary

DS70264B-page 145

dsPIC33FJ12GP201/202

15.5

I2C Module Addresses

The 10-bit I2CxADD register contains the Slave mode

addresses.

If the A10M bit (I2CxCON<10>) is ‘0’, the address is

interpreted by the module as a 7-bit address. When an

address is received, it is compared to the 7 Least

Significant bits of the I2CxADD register.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it is

compared with the binary value, ‘11110 A9 A8’

(where ‘A9’ and ‘A8’ are two Most Significant bits of

I2CxADD). If that value matches, the next address will

be compared with the Least Significant 8 bits of

I2CxADD, as specified in the 10-bit addressing

protocol.

TABLE 15-1:

7-BIT I2C™ SLAVE

ADDRESSES SUPPORTED BY

dsPIC33FJ12GP201/202

15.6

Slave Address Masking

The I2CxMSK register (Register 15-3) designates

address bit positions as “don’t care” for both 7-bit and

10-bit Address modes. Setting a particular bit location

(= 1) in the I2CxMSK register causes the slave module

to respond, whether the corresponding address bit

value is a ‘0’ or ‘1’. For example, when I2CxMSK is set

to ‘00100000’, the Slave module will detect both

addresses, ‘0000000’ and ‘00100000’.

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

15.7

IPMI Support

The control bit IPMIEN enables the module to support

the Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

15.8

General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an Acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R_W = 0.

The general call address is recognized when the

General

Call

Enable

(GCEN)

bit

set

(I2CxCON<7> = 1). When the interrupt is serviced, the

source for the interrupt can be checked by reading the

contents of the I2CxRCV to determine if the address

was device-specific or a general call address.

15.9

Automatic Clock Stretch

In Slave modes, the module can synchronize buffer

reads and write to the master device by clock stretching.

15.9.1

TRANSMIT CLOCK STRETCHING

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared,

indicating the buffer is empty.

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit. The user’s

ISR must set the SCLREL bit before transmission is

allowed to continue. By holding the SCLx line low, the

user application has time to service the ISR and load

the contents of the I2CxTRN before the master device

can initiate another transmit sequence.

15.9.2

RECEIVE CLOCK STRETCHING

The STREN bit in the I2CxCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCLx pin will be held low at

the end of each data receive sequence.

The user’s ISR must set the SCLREL bit before

reception is allowed to continue. By holding the SCLx

line low, the user application has time to service the

ISR and read the contents of the I2CxRCV before the

master device can initiate another receive sequence.

This prevents buffer overruns.

15.10 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the software can clear the

SCLREL bit to allow software to control the clock

stretching.

If the STREN bit is ‘0’, a software write to the SCLREL

bit is disregarded and has no effect on the SCLREL bit.

0x00

General call address or Start byte

0x01-0x03

Reserved

0x04-0x07

Hs mode Master codes

0x08-0x77

Valid 7-bit addresses

0x78-0x7b

Valid 10-bit addresses

(lower 7 bits)

0x7c-0x7f

Reserved

DSPIC33FJ12GP201TE/ML Datasheet(PDF) 147 Page - Microchip Technology

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