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DM3725CBC Datasheet(PDF) 241 Page - Texas Instruments |
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DM3725CBC Datasheet(HTML) 241 Page - Texas Instruments |
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241 / 280 page ![]() SWPS038-090 1-WIRE t RSTH t PDL t PDH t RTSL SWPS038-091 1-WIRE t LOWR t REL t SLOT t RDV t REC 1-WIRE t LOW1 t SLOT t REC SWPS038-123 1-WIRE t LOW0 t SLOT t REC SWPS038-124 DM3730, DM3725 www.ti.com SPRS685D – AUGUST 2010 – REVISED JULY 2011 Table 6-103. HDQ/1-Wire Timing Requirements —1-Wire Mode PARAMETER DESCRIPTION MIN TYP MAX UNIT tPDH Presence pulse delay high 15 60 μs tPDL Presence pulse delay low 60 240 μs tRDV Read data valid time tLOWR 15 μs tREL Read data release time 0 45 μs Table 6-104. HDQ/1-Wire Switching Characteristics —1-Wire Mode PARAMETER DESCRIPTION MIN TYP MAX UNIT tRSTL Reset time low 480 960 μs tRSTH Reset time high 480 μs tSLOT Bit cycle time 60 120 μs tLOW1 Write bit-one time 1 15 μs tLOW0 Write bit-zero time(2) 60 120 μs tREC Recovery time 1 μs tLOWR Read bit strobe time(1) 1 15 μs (1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window. (2) tLOW0 must be less than tSLOT. Figure 6-60. 1-Wire Reset Timing Figure 6-61. 1-Wire Read Bit Timing (Data) Figure 6-62. 1-Wire Write Bit-One Timing (Command / Address or Data) Figure 6-63. 1-Wire Write Bit-Zero Timing (Command/Address or Data) Copyright © 2010–2011, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 241 Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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