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EP2SGX30C Datasheet(PDF) 10 Page - Altera Corporation |
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EP2SGX30C Datasheet(HTML) 10 Page - Altera Corporation |
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10 / 316 page  2–2 Altera Corporation Stratix II GX Device Handbook, Volume 1 October 2007 Transceivers There are up to 20 transceiver channels available on a single Stratix II GX device. Table 2–1 shows the number of transceiver channels and their serial bandwidth for each Stratix II GX device. Figure 2–2 shows the elements of the transceiver block, including the four transceiver channels, supporting logic, and I/O buffers. Each transceiver channel consists of a receiver and transmitter. The supporting logic contains two transmitter PLLs to generate the high-speed clock(s) used by the four transmitters within that block. Each of the four transmitter channels has its own individual clock divider. The four receiver PLLs within each transceiver block generate four recovered clocks. The transceiver channels can be configured in one of the following functional modes: ■ PCI Express (PIPE) ■ OIF CEI PHY Interface ■ SONET/SDH ■ Gigabit Ethernet (GIGE) ■ XAUI ■ Basic (600 Mbps to 3.125 Gbps single-width mode and 1 Gbps to 6.375 Gbps double-width mode) ■ SDI (HD, 3G) ■ CPRI (614 Mbps, 1228 Mbps, 2456 Mbps) ■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps) Table 2–1. Stratix II GX Transceiver Channels Device Number of Transceiver Channels Serial Bandwidth (Full Duplex) EP2SGX30C 4 51 Gbps EP2SGX60C 4 51 Gbps EP2SGX30D 8 102 Gbps EP2SGX60D 8 102 Gbps EP2SGX60E 12 153 Gbps EP2SGX90E 12 153 Gbps EP2SGX90F 16 204 Gbps EP2SGX130G 20 255 Gbps |
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