18F8680 datasheet(133/496 Pages) MICROCHIP

133 / 496 page

 2004 Microchip Technology Inc.

DS30491C-page 131

PIC18F6585/8585/6680/8680

10.3

PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATC) is also memory mapped.

Read-modify-write operations on the LATC register read

and write the latched output value for PORTC.

PORTC is multiplexed with several peripheral functions

(Table 10-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

RC1 is normally configured by configuration bit,

CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = 1).

EXAMPLE 10-3:

INITIALIZING PORTC

FIGURE 10-8:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

CLRF

LATC

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISC

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

PORTC/Peripheral Out Select

Data Bus

WR LATC

WR TRISC

Data Latch

TRIS Latch

RD TRISC

Peripheral Data Out

VDD

VSS

RD PORTC

Peripheral Data In

I/O pin(1)

WR PORTC

RD LATC

Schmitt

Trigger

Note

1: I/O pins have diode protection to VDD and VSS.

2: Peripheral output enable is only active if peripheral select is active.

TRIS

Override

Peripheral Output

Logic

TRIS OVERRIDE

Override

Peripheral

RC0

Yes

Timer1 Osc for

Timer1/Timer3

RC1

Yes

Timer1 Osc for

Timer1/Timer3,

CCP2 I/O

RC2

Yes

CCP1 I/O

RC3

Yes

SPI/I2C

Master Clock

RC4

Yes

I2C Data Out

RC5

Yes

SPI Data Out

RC6

Yes

USART Async

Xmit, Sync Clock

RC7

Yes

USART Sync

Data Out

Enable(2)

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