18F8680 datasheet(151/496 Pages) MICROCHIP

151 / 496 page

 2004 Microchip Technology Inc.

DS30491C-page 149

PIC18F6585/8585/6680/8680

10.9

PORTJ, TRISJ and LATJ

Registers

PORTJ is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISJ. Setting a

TRISJ bit (= 1) will make the corresponding PORTJ pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISJ bit (= 0) will

make the corresponding PORTJ pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATJ) is also memory

mapped. Read-modify-write operations on the LATJ

PORTJ.

PORTJ is multiplexed with the system bus as the

external memory interface; I/O port functions are only

available when the system bus is disabled. When

operating as the external memory interface, PORTJ

provides the control signal to external memory devices.

The RJ5 pin is not multiplexed with any system bus

functions.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTJ pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS

bit settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

EXAMPLE 10-9:

INITIALIZING PORTJ

FIGURE 10-25:

PORTJ BLOCK DIAGRAM

IN I/O MODE

Note:

PORTJ is available only on PIC18F8X8X

devices.

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

CLRF

PORTJ

; Initialize PORTG by

; clearing output

; data latches

CLRF

LATJ

; Alternate method

; to clear output

; data latches

MOVLW

0CFh

; Value used to

; initialize data

; direction

MOVWF

TRISJ

; Set RJ3:RJ0 as inputs

; RJ5:RJ4 as output

; RJ7:RJ6 as inputs

Data

Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

Schmitt

Trigger

Input

Buffer

I/O pin(1)

RD LATJ

PORTJ

Note 1: I/O pins have diode protection to VDD and VSS.

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