18F8680 datasheet(178/496 Pages) MICROCHIP

178 / 496 page

PIC18F6585/8585/6680/8680

DS30491C-page 176

 2004 Microchip Technology Inc.

16.1

ECCP Outputs

The enhanced CCP module may have up to four

outputs depending on the selected operating mode.

These outputs, designated P1A through P1D, are

multiplexed with I/O pins RC2, RE6, RE5 and RG4.

The pin assignments are summarized in Table 16-1.

To configure I/O pins as PWM outputs, the proper PWM

mode must be selected by setting the P1Mx and

CCP1Mx bits (CCP1CON<7:6> and <3:0>, respec-

tively). The appropriate TRIS direction bits for the port

pins must also be set as outputs.

TABLE 16-1:

PIN ASSIGNMENTS FOR VARIOUS ECCP MODES

FIGURE 16-1:

COMPARE MODE OPERATION BLOCK DIAGRAM

ECCP Mode

CCP1CON

Configuration

RC2

RE6

RE5

RG4

Compatible CCP

00xx11xx

CCP1

RE6

RE5

RG4

Dual PWM

10xx11xx

P1A

P1B(2)

RE5

RG4

Quad PWM

x1xx11xx

P1A

P1B(2)

P1C(2)

P1D

Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

Note 1:

TRIS register values must be configured appropriately.

On PIC18F8X8X devices, these pins can be alternately multiplexed with RH7 or RH6 by changing the

ECCPMX configuration bit.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Set Flag bit CCP1IF

Match

RB3/CCP1/P1A pin

TRISB<3>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

Reset Timer1 or Timer3, but will not set Timer1 or Timer3 interrupt flag bit

and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion.

TMR3H

TMR3L

T3CCP2

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