AM79C976 datasheet(155/309 Pages) AMD

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Am79C976

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P R E L I M INARY

INTEN0: Interrupt0 Enable

Offset 040h

This register allows the software to specify which types

of interrupt events will cause the INTR bit in the

Interrupt0 register to be set, which in turn will cause

INTA pin to be asserted if the INTREN bit in CMD0 is

set. Each bit in this register corresponds to a bit in the

Interrupt0 register. Setting a bit in this register enables

the corresponding bit in the Interrupt0 register to cause

the INTR bit to be set.

INTEN0 is a command style register. The high order bit

of each byte of this register is a ’value’ bit that specifies

the value that will be written to selected bits of the reg-

ister. The seven low order bits of each byte make up a

bit map that selects which register bits will be altered.

All bits in this register are cleared to 0 by H_RESET. All

bits are also cleared before EEPROM data are loaded

or after an EEPROM read failure.

The RINTEN and TINTEN bits are set after S_RESET

(but not H_RESET).

Table 60. INTEN0: Interrupt0 Enable Register

Bit

Name

Description

VAL3

Value bit for byte 3. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[30:24] bit map field that are set to 1.

30-28

RES

Reserved locations. Written as zeros and read as undefined.

LCINTEN

Link Change Interrupt Enable. When this bit is set, the INTR bit will be set when the LCINT bit in

INT0 is set.

APINT5EN

Auto-Poll Interrupt from Register 5 Enable. When this bit is set, the INTR bit will be set when the

APINT5 bit in INT0 is set.

APINT4EN

Auto-Poll Interrupt from Register 4 Enable. When this bit is set, the INTR bit will be set when the

APINT4 bit in INT0 is set.

APINT3EN

Auto-Poll Interrupt from Register 3 Enable. When this bit is set, the INTR bit will be set when the

APINT3 bit in INT0 is set.

VAL2

Value bit for byte 2. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[22:16] bit map field that are set to 1.

APINT2EN

Auto-Poll Interrupt from Register 2 Enable. When this bit is set, the INTR bit will be set when the

APINT2 bit in INT0 is set.

APINT1EN

Auto-Poll Interrupt from Register 1 Enable. When this bit is set, the INTR bit will be set when the

APINT1 bit in INT0 is set.

APINT0EN

Auto-Poll Interrupt from Register 0 Enable. When this bit is set, the INTR bit will be set when the

APINT0 bit in INT0 is set.

MIIPDTINTEN

MII PHY Detect Transition Interrupt Enable. When this bit is set, the INTR bit will be set when the

MIIPDTINT bit in INT0 is set.

This bit is an alias of CSR7, bit 0.

MCCIINTEN

MII Management Command Complete Internal Interrupt Enable. When this bit is set, the INTR bit

will be set when the MCCIINT bit in INT0 is set.

This bit is an alias of CSR7, bit 2.

MCCINTEN

MII Management Command Complete Interrupt Enable. When this bit is set, the INTR bit will be

set when the MCCINT bit in INT0 is set.

This bit is an alias of CSR7, bit 4.

MREINTEN

MII Management Read Error Interrupt Enable. When this bit is set, the INTR bit will be set when

the MREINT bit in INT0 is set.

This bit is an alias of CSR7, bit 8

VAL1

Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[14:8] bit map field that are set to 1.

SPNDINTEN

Suspend Interrupt Enable. When this bit is set, the INTR bit will be set when the SPNDINT bit in

INT0 is set.

AM79C976 Datasheet(PDF) 155 Page - Advanced Micro Devices

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