STM32F103RG datasheet(101/120 Pages) STMICROELECTRONICS

101 / 120 page

STM32F103xF, STM32F103xG

Electrical characteristics

Doc ID 16554 Rev 3

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5.3.19

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 62 are preliminary values derived

from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 10.

Note:

It is recommended to perform a calibration after each power-up.

Table 62.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

VREF+

Positive reference voltage

2.4

VDDA

IVREF

Current on the VREF input

-160

220(1)

µA

fADC

ADC clock frequency

0.6

MHz

(2)

Sampling rate

0.05

MHz

fTRIG

(2)

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range(3)

0 (VSSA or VREF-

tied to ground)

-VREF+

RAIN

(2)

External input impedance

See Equation 1 and

Table 63 for details

RADC

(2)

Sampling switch resistance

CADC

(2)

Internal sample and hold

capacitor

tCAL

(2)

Calibration time

fADC = 14 MHz

5.9

µs

1/fADC

tlat

(2)

Injection trigger conversion

latency

fADC = 14 MHz

0.214

µs

3(4)

1/fADC

tlatr

(2)

Regular trigger conversion

latency

fADC = 14 MHz

0.143

µs

2(4)

1/fADC

(2)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB

(2)

Power-up time

µs

tCONV

(2)

Total conversion time

(including sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

Based on characterization, not tested in production.

Guaranteed by design, not tested in production.

VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.

Refer to Section 3: Pinouts and pin descriptions for further details.

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62.

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