STM32F207IC datasheet(135/178 Pages) STMICROELECTRONICS

135 / 178 page

DocID15818 Rev 11

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STM32F20xxx

Electrical characteristics

177

Synchronous waveforms and timings

Figure 60 through Figure 63 represent synchronous waveforms and Table 77 through

Table 79 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

BurstAccessMode = FSMC_BurstAccessMode_Enable;

•

MemoryType = FSMC_MemoryType_CRAM;

•

WriteBurst = FSMC_WriteBurst_Enable;

•

CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)

•

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period.

Figure 60. Synchronous multiplexed NOR/PSRAM read timings

FSMC_CLK

FSMC_NEx

FSMC_NADV

FSMC_A[25:16]

FSMC_NOE

FSMC_AD[15:0]

AD[15:0]

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tw(CLK)

Data latency = 0

BUSTURN = 0

td(CLKL-NExL)

td(CLKL-NExH)

td(CLKL-NADVL)

td(CLKL-AV)

td(CLKL-NADVH)

td(CLKL-AIV)

td(CLKH-NOEL)

td(CLKL-NOEH)

td(CLKL-ADV)

td(CLKL-ADIV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14893h

STM32F207IC Datasheet(PDF) 135 Page - STMicroelectronics

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